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SP8855D 12 package details dimensions are shown thus: mm (in). for further package information please contact your local customer service centre. index corner 17.27/17.78 (0.680/0.700) 16.33/16.81 (0.643/0.662) 1.27/(0.050) nom 1.02mm/(0.040 )nom 45 at 3 places 0.51 (0.02) nom at 45 16.33/16.81 (0.643/0.662) 17.27/17.78 (0.680/0.700) 12.45/12.95 (0.490/0.510) 12.45/12.95 (0.490/0.510) 15.49/16.51 (0.610/0.650) 0.76mm(0.030 ) 0.43mm(0.017 ) 0.89(0.035) 03.05/3.43 (0.120/0.135) hc44 multilayer ceramic j leaded chip carrier headquarters operations gec plessey semiconductors cheney manor, swindon, wiltshire united kingdom sn2 2qw. tel: (01793) 518000 fax: (01793) 518411 gec plessey semiconductors p.o. box 660017 1500 green hills road, scotts valley, california 950670017, united states of america. tel: (408) 438 2900 fax: (408) 438 5576 this publication is issued to provide information only, which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. the company reserves the right to alter without prior notice the specification, design, or price of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to the company's conditions of sale, which are available on request. gec plessey semiconductors 1995 publication no. d.s. 3702 issue no. 2.6 october 1995 customer service centres france & benelux les ulis cedex tel: (1) 64 46 23 45 fax: (1) 69 18 90 00 germany munich tel: (089) 3609 06 0 fax: (089) 3609 06 55 italy milan tel: (02) 66040867 fax: (02) 66040993 japan tokyo tel: (03) 52765501 fax: (03) 52765510 north america scotts valley, usa tel: (408) 438 2900 fax: (408) 438 7023 south east asia singapore tel: (65) 3827708 fax: (65) 3828872 sweden stockholm tel: 46 8 7029770 fax: 46 8 6404736 taiwan , roc taipei tel: 886 2 5461260 fax: 886 2 7190260 uk, eire, denmark, finland & norway swindon tel: (01793) 518527/518566 fax: (01793) 518582 these are supported by agents and distributors in major countries worldwide. technical documentation not for resale. printed in united kingdom
SP8855D 11 from charge pump reference c 1 c 2 r 2 to vco from charge pump output fig. 8 third order loop filter circuit diagram + loop filter design generally the third order filter configuration shown in fig.7 gives better results than the more commonly used second order because the reference sidebands are reduced. three equations are required to determine values for the three constants where; 1 = c 1 2 = r 2 (c 1 + c 2 ) 3 = c 2 r 2 the equations are; 1 2 1 n 2 3 2 3 tan 0 1 cos 0 n 3 1 k k 0 n n 2 1 n 2 2 2 1 n 2 3 2 where; k is the phase detector gain factor in ma/radian k 0 is the vco gain factor in radian/second/volt n is the total division ratio from vco to reference frequency n is the natural loop bandwidth 0 is the phase margin normally set to 45 since the phase detector is linear over a range of 2 radian, k can be calculated from k = phase comparator current setting/2 ma/radian these values can now be substituted in equation 1 to obtain a value for c 1 and equation 2 and 3 used to determine values for c 2 and r 2 example calculate values for a loop with the following parameters frequency to be synthesised: 1000mhz reference frequency 10mhz division ratio 1000mhz/10mhz = 100 n natural loop frequency 100khz k 0 vco gain factor 2 x 10mhz/volt 0 phase margin 45 phase comparator current 6.3ma the phase detector gain factor k = 6.3ma /2 = 1ma/radian from equation 3: 3 tan 45 1 cos 45 100khz 2 0 . 4142 628319 from equation 2: 2 1 (100khz 2 ) 2 659 10 9 2 3 . 844 10 6 using these values in equation 1: 1 1x10 3 2 10mhz v 100 (2 100khz) 2 [ a ] 659 10 9 where a is : 1 1.59 10 9 x 2 . 415 1 3.84 10 9 now 1 c 1 c 1 3 . 84nf 2 r 2 (c 1 c 2 ) 3 c 2 r 2 1

1 n 2 1 n 2 ( 2 100k ) 2 ( 3 . 844 x 10 6 ) 2 1 ( 2 100k ) 2 ( 659 x 10 9 ) 2 substituting for c 2 2 2 r 2 c 1 3
829
0.794
SP8855D 10 gain can be modified when new frequency data is entered to compensate for change in the vco gain characteristic over its frequency band. the charge pump pulse current is determined by the current fed into pin 19 and is approximately equal to pin 19 current when the programmed multiplication ratio is one. the circuit diagram fig. 7e shows the internal components on pin 19 which mirror the input current into the charge pump. the voltage at pin 19 will be approximately 1.6v above ground due to two v be drops in the current mirror. this voltage will exhibit a negative temperature coefficient, causing the charge pump current to change with chip temperature by up to 10% over the full military temperature range if the current programming resistor is connected to v cc as shown in the application diagram fig. 5. in critical applications where this change in charge pump current would be too large the resistor to pin 19 could be increased in value and connected to a higher supply to reduce the effect of v be variation on the current level. a suitable resistor connected to a 30v supply would reduce the variation in pin 19 current due to temperature to less than 1.5%. alternatively a stable current source could be used to set pin 19 current. the charge pump output on pin 20 will only produce symmetrical up and down currents if the voltage is equal to that on the voltage reference pin 21. in order to ensure that this voltage relationship is maintained, an operational amplifier must be used as shown in the typical application fig. 5. using this configuration pin 20 voltage will be forced to be equal to that on pin 21 since the operational amplifier differential input voltage will be no more than a few millivolts (the input offset voltage of the amplifier). when the synthesiser is first switched on or when a frequency outside the vco range is programmed the amplifier output will limit, allowing pin 20 voltage to differ from that on pin 21. as soon as an achievable frequency value is programmed and the amplifier output starts to slew the correct voltage relationship between pin 20 and 21 will be restored. because of the importance of voltage equality between the charge pump reference and output pins, a resistor should never be connected in series with the operational amplifier inverting input and pin 20 as is the case with a phase detector giving voltage outputs. any current drawn from the charge pump reference pin should be limited to the few micro amps input current of a typical operational amplifier. a resistor between the charge pump reference and the non inverting input could be added to provide isolation but the value should not be so high that more than a few millivolts drop are produced by the amplifier input current. when selecting a suitable amplifer for the loop filter, a number of parameters are important; input offset voltage in most designs is only a few milivolts and an offset of 5mv will produce a mismatch in the up and down currents of about 4% with the charge pump multiplication factor set at 1. the mismatch in up down currents caused by input offset voltage will be reduced in proportion to the charge pump multiplication factor in use. if the linearity of the phase detector about the normal phase locked operating point is critical, the input offset voltage of most amplifiers can be adjusted to near zero by means of a potentiometer. the charge pump reference voltage on pin 21 is about 1.3v below the positive supply and will change with temperature and with the programmed charge pump multiplication factor. in many cases it is convenient to operate the amplifier with the negative power supply pin connected to 0v as this removes the need for an additional power supply. the amplifier selected must have a common mode range to within 3.4v (minimum charge pump reference voltage) of the negative supply pin to operate correctly without a negative supply. most popular amplifiers can be operated from a 30v positive supply to give a wide vco voltage drive range and have adequate common mode range to operate with inputs at +3.4v with respect to the negative supply. input bias and offset current levels to most operational amplifiers are unlikely to be high enough to significantly affect the accuracy of the charge pump circuit currents but the bias current can be important in reducing reference side bands and local oscillator drift during frequency changes. when the loop is locked, the charge pump produces only very narrow pulses of sufficient width to make up for any charge lost from the loop filter components during the reference cycle. the charge lost will be due to leakage from the charge pump output pin and to the amplifier input bias current, the latter usually being more significant. the result of the lost charge is a sawtooth ripple on the vco control line which frequency modulates the phase locked oscillator at the reference frequency and its harmonics. it is possible to disable the charge pump by taking pin 39 low. in this case any leakage current will cause the oscillator to drift off frequency. this feature may be useful where having acheived lock an external phase detector of the user's choice can be employed to suit a specific application. f pd and f ref outputs these outputs provide access to the outputs from the rf and reference dividers and are provided for monitoring purposes during product development or test, and for connection of an external phase detector if required. the output circuit is of ecl type, the circuit diagram being shown in fig.7g. the outputs can be enabled or disabled under software control by the address 0 control word but are best left in the disabled state when not required as the fast edge speeds on the output can increase the level of reference sidebands on the synthesised oscillator. the emitter follower outputs have no internal pull down resistor to save current and if the outputs are required an external pull down resistor should be fitted.the value should be kept as high as possible to reduce supply current, about 2.2k being suitable for monitoring with a high impedance oscilloscope probe or for driving an ac coupled 50ohm load. a minimum value for the pull down resistor is 330ohms. when the f pd and f ref outputs are disabled the output level will be at the logic low level of about 3.5v so that the additional supply current due to the load resistors will be present even when the outputs are disabled. reference input the reference input circuit functions as an input amplifier or crystal oscillator. when an external reference signal is used this is simply ac coupled to pin 28, the base of the input emitter follower. when a low phase noise synthesiser is required the reference signal is critical since any noise present here will be multiplied by the loop. to obtain the lowest possible phase noise from the SP8855D it is best to use the highest possible reference input frequency and to divide this down internally to obtain the required frequency at the phase detector. the amplitude of the reference input is also important, and a level close to the maximum will give the lowest noise. when the use of a low reference input frequency say 410mhz is essential some advantage may be gained by using a limiting amplifier such as a cmos gate to square up the reference input. in cases where a suitable reference signal is not available, it may be more convenient to use the input buffer as a crystal oscillator in this case the emitter follower input transistor is connected as a colpitts oscillator with the crystal connected from the base to ground and with the feedback necessary for oscillation provided by a capacitor tap at the emitter. the arrangement is shown inset in fig. 5.
SP8855D 9 v cc 3.3ma 0v 296 fig. 7g f pd and f ref outputs 296 296 24, 25 f pd, f ref 40k 28 27 oscillator capacitor oscillator crystal 60k 100 a 60k 40k 50 a50 a 100 a 3k 3k 100 a v cc 0v fig. 7h reference oscillator fig. 7 interface circuit diagrams (cont) outputs applications rf layout the SP8855D can operate with input frequencies up to 1.7ghz but to obtain optimum performance, good rf layout practices should be used. a suitable layout technique is to use double sided printed board with through plated holes. wherever possible the top surface on which the SP8855D is mounted should be left as a continuous sheet of copper to form a low impedance earth plane. the ground pins 12 and 16 should be connected directly to the earth plane. pins such as v cc and the unused rf input should be decoupled with chip capacitors mounted as close to the device pin as possible with a direct connection to the earth plane, suitable values are 10nf for the power supplies and <1nf for the rf input pin. (a lower value should be used sufficient to give good decoupleing at the rf frequnecy of operation). a larger decoupling capacitor mounted as close as possible to pin 26 should be used to prevent modulation of v cc by the charge pump pulses. the r set resistor should also be mounted close to the r set pin to prevent noise pickup, and the capacitor connected from the charge pump output should be a chip component with short connections to the SP8855D. when the reference is derived from a crystal connected to pins 27 and 28 as shown in fig. 5 the oscillator components are best mounted close to the SP8855D. all signals such as the programming inputs, rf in, reference in and the connections to the opamp are best taken through the pc board adjacent to the SP8855D with through plated holes allowing connections to remote points without fragmenting the earth plane. programming inputs the input pins are designed to be compatible with ttl or cmos logic with a switching threshold set at about 2.4v by three forward biased base emitter diodes. the inputs will be taken high by an internal pull up resistor if left open circuit but for best noise immunity it is better to connect unused inputs directly to v cc or ground. rf inputs the prescaler has a differential input amplifer to improve input sensitivity. generally the input drive will be single ended and the rf signal should be ac coupled to either of the inputs using a chip capacitor. the remaining input should be decoupled to ground, again using a chip capacitor. the inputs can be driven differentially but the input circuit should not provide a dc path between inputs or to ground. lock detect circuit the lock detect circuit uses the up and down correction pulses from the phase detector to determine whether the loop is in or out of lock. when the loop is locked, both up and down pulses are very narrow compared to the reference frequency, but the pulse width in the out of lock condition continuously varies, depending on the phase difference between the outputs of the reference and rf counters. the logical and of the up and down pulses is used to switch a 20ma current sink to pin 18 and a 50k resistor provides a load to v cc . the circuit is shown in fig. 7c. when lock is established, the narrow pulses from the phase detector ensure that the current source is off for the majority of the time and so pin 18 will be pulled high by the 50k resistor. a voltage comparator with a switching threshold at about 4.7v monitors the voltage at pin 18 and switches pin 17 low when pin 18 is more positive than the 4.7v threshold. when the loop is unlocked, the frequency difference at the counter outputs will produce a cyclic change in pulse width from the phase detector outputs with a frequency equal to the difference in frequency at the reference and rf counter outputs. a small capacitor connected to pin 18 prevents the indication of false phase lock conditions at pin 17 for momentary phase coincidence. because of the variable width pulse nature of the signal at pin 18 the calculation of a suitable capacitor value is complex, but if an indication with a delay amounting to several times the expected lock up time is acceptable, the delay will be approximately equal to the time constant of the capacitor on pin 18 and the internal 50k resistor. if a faster indication is required, comparable with the loop lock up time, the capacitor will need to be 23 times smaller than the time constant calculation suggests. the time to respond to an out of lock condition is 23 times less than that required to indicate lock. charge pump circuit the charge pump circuit converts the variable width up and down pulses from the phase detector into adjustable current pulses which can be directly connected to the loop amplifer. the magnitude of the current and therefore the phase detector
SP8855D 8 40k 40k 5k 5k v cc input 50 a 0v 4k 325 325 v cc 3ma 0v rf input rf input 13 14 3k 500 500 fig. 7a rf and reference divider programming bits, f pd /f ref enable, control direction and phase detector gain control inputs fig. 7b rf inputs fig. 7 interface circuit diagrams fig. 7c lock detect decouple v cc 100 a clock detect (high when locked) 18 3k 50k 3k v ref 4.7v 20 a 0v 2k5 2k5 3k 3k low when locked lock detect output 17 400 a 100 100 0v fig. 7d lock detect output 1k 11 v cc v cc r set 19 130 charge pump current sources fig. 7e r set pin. v cc v cc 20 21 450 83 83 2ma up down reference charge pump output 450 fig. 7f charge pump circuit
SP8855D 7 pin 40 pin 41 current multiplication factor 0 0 1.0 0 1 1.5 1 0 2.5 1 1 4.0 table 1 pin 19 current v cc 1.6v r set i pin 19 (ma) multiplication factor 2 ma radian phase detector gain to allow for control direction changes introduced by the design of the pll, pin 23 can be programmed to reverse the control direction of the loop by transposing the f pd and f ref connections. in order that any external phase detector will also be reversed by this function, the f pd and f ref outputs are also interchanged as shown in table 2. output for rf phase lag control direction pin 23 pin 20 1 current source 0 current sink table 2 the f pd and f ref signals to the phase detector are available on pin 24 and 25 and may be used to monitor the frequency input to the phase detector or used in conjunction with an external phase detector. when the f pd /f ref outputs are to be used at high frequencies, an external pull down resistor of minimum value 330 may be used connected to ground to reduce the fall time of the output pulse. the charge pump connections to the loop amplifier consist of the charge pump output and the charge pump reference. the matching of the charge pump up and down currents will only be maintained if the charge pumps output is held at a voltage equal to the charge pump reference using an operational amplifier to produce a virtual earth condition at pin 20. the lock detect circuit can drive an led to give visual indication of phase lock or provide an indication to the control system if a pull up resistor is used in place of the led. a small capacitor connected from the clock detector pin to ground may be used to delay lock detect indication and remove glitches produced by momentary phase coincidence during lock up. the phase detector can be disabled by pulling pin 39 to logic low. reference divider programming pin allocation ten bit reference counter 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 pin 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 phase detector gain control m counter 3 bit a counter 2 13 2 10 2 11 2 12 rf divider programming pin allocation fig. 6 programming data format 29 30 31 32 33 34 35 36 37 38 pin 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 see table 1
SP8855D 6 application using crystal reference rf counter programming 1k 1n vco sp8855 * values depend 33p 10mhz crystal 100p 1n 10n * 100p 1 fref fpd 2k2 10n 1n * * * 27 28 SP8855D on application loop filter op27 etc +5v 100n +30v ref in 43 42 41 39 38 37 36 35 34 33 32 31 30 29 40 28 27 26 25 24 23 22 21 20 19 18 7 8 9 10 11 12 13 14 15 16 17 44 1 2 3 4 5 6 fig. 5 typical application diagram v cc v cc reference counter programming + description prescaler and am counter the programmable divider chain is of a m counter construction and therefore contains a dual modulus front end prescaler, an a counter which controls the dual modulus ratio and an m counter which performs the bulk multimodulus division. a programmable divider of this construction has a division ratio of mn+a and a minimum integer steppable division ratio of n(n1), where n is the prescaler ratio. programming the device is programmed by connecting the programming pins to either v cc or ground. the programming inputs will go high if left open circuit but for best noise immunity a wired connection to v cc is preferable. the programming inputs can be driven from ttl or cmos logic levels if required. reference input the reference source can be either driven from an external sine or square wave source of up to 100mhz or a crystal can be connected as shown in fig. 5. phase comparator and charge pump the SP8855D has a digital phase/frequency comparator driving a charge pump with programmable current output. the charge pump current level at the minimum gain setting is approximately equal to the current fed into the r set input pin 19 and can be increased by programming pins 40 and 41 according to table 1 by up to 4 times.
SP8855D 5 +20 +10 10 20 1ghz 2ghz 10ghz input drive requirements fig. 3 SP8855D 30 100mhz +7 5 guaranteed operating window typical sensitivity typical overload input to pin13 (dbm) 1.7ghz 0.5 0.2 1 0 +j0.2 +j0.5 +j1 +j2 +j5 2 5 j5 j2 j1 j0.5 j0.2 fig. 4 r.f. input impedance 50mhz 1.1ghz zo=50 2.5ghz
SP8855D 4 electrical characteristics guaranteed over the full temperature and supply voltage range (unless otherwise stated) temperature t amb for kg parts 55 c and +100 c temperature t amb for ig parts 40 c and +85 supply voltage = 4.75v and 5.25v characteristics pin value units conditions ch aracter i st i cs pi n min typ max u n i ts c on di t i ons supply current 15, 26 180 240 ma rf input sensitivity 13, 14 5.0 +7.0 dbm 100mhz to 1.7ghz see fig. 3 rf division ratio 13,14,24 56 16383 reference division ratio 28, 25 1 1023 comparison frequency 28,24,25 50 mhz reference input frequency 28 10 100 mhz reference division ratio 2 see note 1 reference input voltage 28 0 +6 +10 dbm f ref /f pd output voltage high 24, 25 0.8 vwrt v cc 2.2k to 0v f ref /f pd output voltage low 24, 25 1.4 vwrt v cc 2.2k to 0v lock detect output voltage 17 300 500 mv i out = 3ma charge pump current at multiplication factor =1 19,20,21 1.4 1.5 1.7 ma v pin 20 = v pin 21 , i pin 19 = 1.6ma charge pump current at multiplication factor =1.5 19,20,21 2.0 2.3 2.5 ma v pin 20 = v pin 21 , i pin 19 = 1.6ma charge pump current at multiplication factor = 2.5 19,20,21 3.4 3.8 4.6 ma v pin 20 = v pin 21 , i pin 19 = 1.6ma charge pump current at multiplication factor = 4.0 19,20,21 5.4 6.1 6.5 ma v pin 20 = v pin 21 , i pin 19 = 1.6ma input bus high logic level 111,22 23,2944 3.5 v input bus low logic level 111,22, 23,2944 1 v input bus current source 111,22, 23,2944 200 a v in = 0v input bus current sink 111,22, 23,2944 10 a v in = v cc up down current matching 20 5 % v pin 20 = v pin 21, i pin 19 = 1.6ma charge pump reference voltage 21 v cc 0.5 v i pin 19 = 1.6ma current multiplication factor = 1 charge pump reference voltage 21 v cc 1.6 v i pin 19 = 1.6ma current multiplication factor = 4 r set current 19 0.5 2 ma see note 2 r set voltage 19 1.6 v i pin 19 = 1.6 ma notes: 1. lower reference frequencies may be used if slew rates are maintained. 2. pin 19 current x multiplication factor must be less than 5ma if charge pump accuracy is to be maintained.
SP8855D 3 pin description pin description 1,2,3,4,5,6,7,8,9,10,11,42,43,44 these pins are the data inputs used to set the rf divider ratio (m.n+a). open circuit=1 (high) on these pins. inputs are transparent into the data buffers. 13, 14 (rf input) balanced inputs to the rf preamplifier. for single ended operation the signal is ac coupled into pin 13 with pin 14 ac decoupled to ground (or viceversa.) pins 13 and 14 are internally dc biased. 17 (lock detect input) a current sink into this pin is enabled when the lock detect circuit indicates lock. used to give an external indication of phase lock. 18 (clock detect) a capacitor connected to this point determines the lock detect integrator time constant and can be used to vary the sensitivity of the phase lock indicator. 19 (rset) an external resistor from pin 19 to v cc sets the charge pump output current. 20 (cp output) the phase detector output is a single ended charge pump sourcing or sinking current to the inverting input of an external loop filter. 21 (cp ref) connected to the noninverting input of the loop filter to set the optimum dc bias. 22 (f ref /f pd enable) part of the data input bus. when this pin is logic hi the f ref and f pd outputs are enabled. open circuit=hi. 23 (control direction) this pin controls charge pump output direction. for pin 23 hi the output sinks current when f pd > f ref or when the rf phase leads ref phase. for pin 23 lo the relationship is reversed. (see table 2). changing the state of pin 23 reverses the pins on which f ref and f pd output occur. see pin 24 and pin 25 below for details. open circuit =hi. 24 =f pd if pin 23 is hi =f ref if pin 23 is lo rf divider output pulses. f pd =rf input frequency/(m.n+a). pulse width=8 rf input cycles (1 cycle of the divide by 8 prescaler output). 25 =f ref if pin 23 is hi =f pd if pin 23 is lo reference divider output pulses. f ref =reference input frequency/r. pulse width =high period of ref input. 27 (reference oscillator capacitor) leave open circuit if an external reference is used. see fig. 5 for typical connection for use as an onboard crystal oscillator. 28 (ref in/xtal) this pin is the input buffer amplifier for an external reference signal. this amplifier provides the active element if an onboard crystal oscillator is used. 29,30,31,32,33,34,35,36,37,38 these pins set the reference divider ratio r. open circuit =hi. 39 (phase detector enable) when this pin is hi the phase detector output is enabled. open circuit =hi. 40, 41 (pd gain) these pins set the charge pump current multiplication factor (see table 1). open circuit =hi.
SP8855D 2 phase reference divider 27 reference crystal reference capacitor f ref * f pd and f ref outputs are reversed using the control direction input . diagram is correct when pin 23 is high. detector v 26 +5v 16 ee 0v f ref * f pd * clock detect r set lock det o/p charge pump reference charge pump output f pd m counter a counter modulus control 8/9 15 13 14 12 v cc +5v prescaler rf input 0v prescaler fig. 2 SP8855D block diagram f pd f ref / enable control direction 10 38 37 36 35 34 33 32 31 30 29 bit 0 bit 9 reference divider programming 11 10 9 b0 b2 phase detector gain 1 phase detector gain 0 28 bit b3 b13 8 7 6 5 4 3 2 1 44 43 42 phase detector enable 20 21 17 19 18 24 25 22 23 40 41 39 3 bit 11 bit rf divider programming
preliminary information october 1995 d.s. 3702 2.6 SP8855D 1.7ghz parallel load professional synthesiser the SP8855D is one of a family of parallel load synthesisers containing all the elements apart from the loop amplifier to fabricate a pll synthesis loop. other parts in the series are the sp8852d which is a fully programmable device requiring two 16 bit words to set the rf and reference counters, and the sp8854d which has hard wired reference counter programming and requires a single bit word to program the rf divider. the SP8855D is intended for applications where a fixed synthesiser frequency is required although it can also be used where frequency selection is set by switches. in general the device will be programmed by connecting the programming pins to either v cc or ground. additional hard wired inputs can be used to control the f pd and f ref outputs, set the control direction of the loop and select the phase detector gain. another input may be used to disable the phase detector output features 1.7ghz operating frequency single 5v supply operation low power consumption <1.3w high comparison frequency 50mhz high gain phase detector 1ma/rad programmable phase detector gain zero ``dead bando phase detector wide range of rf and reference divide ratios programming by hard wired inputs absolute maximum ratings supply voltage 0.3v to 6v storage temperature 65 c to+150 c operating temperature 55 c to+100 c prescaler & reference input voltage 2.5v pp data inputs v cc +0.3v v ee 0.3v junction temperature +175 c ordering information SP8855D kg hcar (non standard temperature range 55 c to +100 c standard product screening) SP8855D ig hcar (industrial temperature range 40 c to +85 c standard product screening) thermal data jc =5 c/w jc =53 c/w esd: 1000v, human body model 144 index corner hc44 pin description pin description 1 input bus bit 10 23 control direction 2 input bus bit 9 24 f pd* 3 input bus bit 8 25 f ref* 4 input bus bit 7 26 +5v 5 input bus bit 6 27 ref. osc capacitor 6 input bus bit 5 28 ref in/xtal 7 input bus bit 4 29 reference bit 9 8 input bus bit 3 30 reference bit 8 9 input bus bit 2 31 reference bit 7 10 input bus bit 1 32 reference bit 6 11 input bus bit 0 33 reference bit 5 12 0v (prescaler) 34 reference bit 4 13 rf input 35 reference bit 3 14 rf input 36 reference bit 2 15 v cc +5v (prescaler) 37 reference bit 1 16 v ee 0v 38 reference bit 0 17 lock detect output 39 phase detect enable 18 clock detect 40 phase detect gain 1. 19 r set 41 phase detect gain 0 20 charge pump output 42 input bus bit 13 21 charge pump ref. 43 input bus bit 12 22 f ref /f pd enable 44 input bus bit 11 fig. 1 pin connections top view * f pd and f ref outputs are reversed using the control direction input. the table above is correct when pin 23 is high.
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